This rule detects addition operations where the result can exceed the representable range of the destination data type, leading to unintended wrap-around (overflow).
In hardware, overflow produces incorrect results silently, violating both functional correctness and security guarantees.
Compatibility matrix:
| VHDL | ✓ |
| Verilog | ✗ |
entity top is
port (
a : in integer;
b : out integer
);
end entity top;
architecture rtl of top is
begin
process (a)
begin
b <= a + 1;
end process;
end architecture rtl;