Why is this an issue?

A solve before constraint nested inside another constraint is not allowed in SystemVerilog. Even if some tools permit it, this structure should be avoided to ensure portability.

How to fix it

Code examples

Noncompliant code example

class A;
  int arr[3];
  rand int a, b;
  constraint C {
    foreach (arr[i]) solve a before b; // Noncompliant
  }
endclass