Why is this an issue?

A signal assigned in an always_latch is assigned on all control paths and so infers combinational logic instead of a latch.

How to fix it

Code examples

Noncompliant code example

module fly(input logic a, output logic b);
  always_latch begin
    b = a;
  end
endmodule

Compliant solution

module fly(input logic a, output logic b);
  always_comb begin
    b = a;
  end
endmodule