Why is this an issue?

A wildcard case statement has a 2-state condition and 2-state items, so there will never be unknown bits and therefore no wildcard matching will occur. If expected, convert this to a normal case statement to better express the intent.

How to fix it

Code examples

Noncompliant code example

module fly;
  bit [2:0] a;
  initial casex (a)
    3'd0:;
    3'd1:;
    default;
  endcase
endmodule

Compliant solution

module fly;
  bit [2:0] a;
  initial case (a)
    3'd0:;
    3'd1:;
    default;
  endcase
endmodule