<h2>Why is this an issue?</h2>
<p>
  A user-defined primitive is edge sensitive but does not provide an output value for all possible edges of all inputs.
  This is not necessarily wrong; the default output value when given unspecified input combinations is <code>x</code>,
  but the LRM mentions this constraint in section 29.6 so this warning can be used if you wish to be pedantic.
  Additionally, it can be useful for checking for missed transitions when developing and simulating the behavioral model
  of industrial cells, which are commonly implemented as Verilog primitives.
</p>

<h2>How to fix it</h2>
<h3>Code examples</h3>
<h4>Noncompliant code example</h4>
<pre>
primitive d_edge_ff (q, clock, data);
  output q; reg q;
  input clock, data;
  table
    // clock data q q+
    // obtain output on rising edge of clock
    (01) 0 : ? : 0 ;
    (01) 1 : ? : 1 ;
    (0?) 1 : 1 : 1 ;
    (0?) 0 : 0 : 0 ;
    // ignore negative edge of clock
    (?0) ? : ? : - ;
    // missed clock edge (1x) specification
    // missed edge specifications for data signal
  endtable
endprimitive
</pre>