Why is this an issue?

Combinational outputs at top level are forbidden. All the output signals of the top-level module should be registered.

How to fix it

Code examples

Noncompliant code example

entity top is
  port(
    clk   : in  std_logic;
    rst   : in  std_logic;
    in_1  : in  std_logic;
    in_2  : in  std_logic;
    out_1 : out std_logic; -- Noncompliant
    out_2 : out std_logic; -- Noncompliant
    out_3 : out std_logic -- Compliant
  );
end;

architecture rtl of top is
  signal s1, s2 : std_logic;
begin
  process(clk) is
  begin
    if rst = '0' then
      s1 <= '0';
      s2 <= '0';
    elsif rising_edge(clk) then
      s1 <= in_1;
      if in_1 = '1' then
        s2 <= in_2;
      end if;
    end if;
  end process;

  out_1 <= s1 and s2; -- Noncompliant: "AND" combinational on output path
  out_2 <= s1 xor s2; -- Noncompliant: "XOR" combinational on output path
  out_3 <= s1; -- Compliant
end;

Resources

Related rules