Why is this an issue?

Output signal that is a constant might be due to an erroneous or incomplete implementation.

How to fix it

Code examples

Noncompliant code example

entity top is
  port(
    clk : in  std_logic;
    i1  : in  std_logic;
    i2  : in  std_logic;
    o1  : out std_logic; -- Compliant
    o2  : out std_logic -- Noncompliant
  );
end;

architecture rtl of top is
begin
  process(clk) is
  begin
    if rising_edge(clk) then
      o1 <= i1 and i2;
      o2 <= '0'
    end if;
  end process;
end;