Why is this an issue?

The preference for asynchronous resets over synchronous resets can be attributed to several key advantages:

1. Predictable Behavior During Power-Up
   • When power is applied or during a reset event, an asynchronous reset will ensure that the flip-flops are reset immediately, regardless of the clock. This can be crucial for ensuring a known state as soon as possible after power-up or reset.
2. Recovery from Unknown States
   • If the system enters an unknown state due to noise or other disturbances, an asynchronous reset can bring the system back to a known state without needing to wait for a clock edge. This can be particularly important in systems where timing margins are tight or where the clock might be unreliable during initial power states.
3. Simplicity in Design
   • Asynchronous resets can simplify the design in some cases because they do not have to align with clock cycles. This can be advantageous if you're dealing with timing issues where clock skew might otherwise affect the reset process.
4. Testing and Debugging
   • Asynchronous resets can sometimes make it easier to control the system state during testing, especially in environments where you might want to halt the system at any point in time, not just on clock edges.

Drawbacks of Asynchronous Resets

• Design Complexity for Timing: While they can simplify some aspects, asynchronous resets can introduce timing complexities, especially in large designs where reset propagation needs careful management to avoid glitches or race conditions.
• Reset Synchronization: If asynchronous resets are used across multiple clock domains, you might still need some level of synchronization to avoid setup and hold time violations, which can complicate the design.
• Verification Challenges: The non-deterministic nature of asynchronous events can make verification more challenging since the exact behavior might depend on the timing of the reset signal relative to the clock.

In summary, while asynchronous resets can offer advantages in terms of predictable power-up behavior and quicker state recovery, they also come with their own set of challenges, particularly related to timing and design complexity. The choice often depends on the specific requirements of the system, the timing constraints, and the design methodology being followed. If your design prioritizes immediate state correction or if you're dealing with scenarios where the clock might not be reliable during reset conditions, asynchronous resets could be the better choice. However, in systems where clock distribution is well-managed and where you want to avoid potential asynchronous timing issues, synchronous resets might be preferred.

How to fix it

Code examples

Noncompliant code example

process (clk) is
begin
 if rising_edge(clk) then
   s <= '1';
   if rst = '1' then  -- Synchronous reset
     s <= '0';
   end if;
 end if;
end process;

Compliant solution

process(clk, rst) is
begin
  if rst = '1' then -- Asynchronous reset
    s <= '0';
  elsif rising_edge(clk) then
    s <= '1';
  end if;
end process;

Resources

Related rules

• Synchronous resets should be preferred over asynchronous resets