Why is this an issue?

SystemVerilog always_comb should be used instead of Verilog always @* or always @(*).

How to fix it

Code examples

Noncompliant code example

always @(*) begin
  b <= a;
  c <= b;
end

always @* begin
  d <= f;
  e <= g;
end

Compliant solution

always_comb begin
  b <= a;
  c <= b;
end

always_comb begin
  d <= f;
  e <= g;
end

Resources

Articles & blog posts