Why is this an issue?

If more than one defparam target the same parameter, the SystemVerilog standard specifies that this is undefined behavior.

Even if synthesizers usually take the value from the first defparam they see, code is not portable and behavior can be inconsistent. Thus, multiple definitions should be avoided to keep your code easy to understand and portable.

How to fix it

Code examples

Noncompliant code example

module fly;
  parameter p = 1;
  parameter q = 1;
endmodule

module dream;
  defparam fly1.p = 3;
endmodule

module top;
  fly fly1();
  dream dream1();
  defparam fly1.p = 2; // Noncompliant
  defparam fly1.q = 2;
endmodule

Compliant solution

module fly;
  parameter p = 1;
  parameter q = 1;
endmodule

module dream;
  defparam fly1.p = 3;
endmodule

module top;
  fly fly1();
  dream dream1();
  defparam fly1.q = 2;
endmodule