Why is this an issue?

According to the Verilog/SystemVerilog standard, it is illegal to procedurally force/release a bit-select or range select of a variable (you can do that with a net, or with a plain variable).

Even if some tools support this syntax, it should be avoided to keep your code portable.

How to fix it

Code examples

Noncompliant code example

module top;
  int i;
  initial begin
    force i[1] = 1; // Noncompliant
    release i[1]; // Noncompliant
  end
endmodule