Why is this an issue?

An implicit conversion in an expression converts between two unrelated types. SystemVerilog allows this for all packed integral types but it often indicates a mistake in the code.

How to fix it

Code examples

Noncompliant code example

module fly;
  struct packed { logic a; int b; } foo;
  union packed { int a; int b; } bar;
  initial foo = bar;
endmodule