Why is this an issue?

A timing control edge expression (posedge, negedge, etc.) is wider than one bit, which can indicate a mistake since only changes to the first bit will trigger the edge.

How to fix it

Code examples

Noncompliant code example

module fly;
  int i;
  always @(posedge i) begin end
endmodule

Compliant solution

module fly;
  logic i;
  always @(posedge i) begin end
endmodule