Why is this an issue?

dist constraint items are not allowed to be surrounded by parentheses according to the SystemVerilog standard.

Even if some tools allow it, refrain from using this syntax to keep your code portable.

How to fix it

Code examples

Noncompliant code example

class Fly;
  rand bit a;
  rand bit [3:0] b;
  constraint cmd_c {
    a -> (b dist { 0 := 1, [1:15] := 1});
  }
endclass

Compliant solution

class Fly;
  rand bit a;
  rand bit [3:0] b;
  constraint cmd_c {
    a -> b dist { 0 := 1, [1:15] := 1};
  }
endclass