Why is this an issue?

State-dependent path conditions in specify blocks are restricted to a subset of expression types and operators (see SystemVerilog standard, Table 30-1 for the list of valid operators).

Even if some tools allow more expression types and operators, stick to the standard to keep your code portable.

How to fix it

Code examples

Noncompliant code example

module fly(input b, output c);
  wire integer a;
  specify
    if (a === 1 + 1) (b => c) = (0,0); // Noncompliant: 'a === 1 + 1' expression is not valid in a state-dependent path condition
  endspecify
endmodule