Why is this an issue?

The SystemVerilog standard disallows using parameters inside of specify blocks.

Even if most tools allow them, stick to the standard to keep your code portable.

How to fix it

Code examples

Noncompliant code example

module fly(input [1:0] a, output [1:0] b);
  parameter p = 1;
  specify
    (a[p] => b[0]) = 1;
  endspecify
endmodule

Compliant solution

module fly(input [1:0] a, output [1:0] b);
  specify
    (a[1] => b[0]) = 1;
  endspecify
endmodule