Why is this an issue?

Top-level entity ports are mapped on real component pins. Restrictions should apply to be sure that these VHDL pins map flawlessly to real pins. Thus, only use the following allowed types:

Low-level entity/component port types are restricted to the following types:

subtypes of those types, records of those types and arrays of those types.

Note that the list of allowed port types can be customized through parameters.

How to fix it

Code examples

Noncompliant code example

With the default values of allowed types: 
entity top is
  port(
    a : in std_logic;
    b : out std_logic_vector(0 to 7);
    c : out integer -- Noncompliant: 'integer' is not part of the allowed types
  );
end;

entity low is
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer; -- Noncompliant: 'integer' is not part of the allowed types
  );
end;

component c
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer; -- Noncompliant: 'integer' is not part of the allowed types
  );
end component;

Compliant solution

With the default values of allowed types: 
entity top is
  port(
    a : in std_logic;
    b : out std_logic_vector(0 to 7)
  );
end;

entity low is
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7)
  );
end;

component c
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
  );
end component;
With custom values of allowed types: 
entity top is
  port(
    a : in std_logic;
    b : out std_logic_vector(0 to 7)
  );
end;

entity low is
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer
  );
end;

component c
  port(
    a : in std_logic;
    c : out std_logic_vector(0 to 7);
    d : out integer
  );
end component;