Why is this an issue?

Sharing some naming conventions is a key point to make it possible for a team to efficiently collaborate. This rule allows to check that all clock signals names match a provided regular expression.

How to fix it

Code examples

Noncompliant code example

With default regular expression: ^[a-z\d_]+_clk)|clk$

entity fly is
  port (
    clk1 : in std_logic; -- Noncompliant: "clk1" does not match "^([a-z\d_]+_clk)|clk$" regular expression
    i1 : in std_logic;
    o1 : out std_logic
  );
end entity;

architecture rtl of fly is
begin
  process (clk1) is
  begin
    if rising_edge(clk1) then
      o1 <= not i1;
    end if;
  end process;
end architecture;

Compliant solution

With default regular expression: ^[a-z\d_]+_clk)|clk$

entity fly is
  port (
    clk : in std_logic; -- Compliant
    i1 : in std_logic;
    o1 : out std_logic
  );
end entity;

architecture rtl of fly is
begin
  process (clk1) is
  begin
    if rising_edge(clk) then
      o1 <= not i1;
    end if;
  end process;
end architecture;