Sharing some naming conventions is a key point to make it possible for a team to efficiently collaborate. This rule allows to check that all enable signals names match a provided regular expression.
With default regular expression: ^[a-z\d_]+_enable)|enable$
entity fly is
port (
clk : in std_logic;
rst : in std_logic;
enable1 : in std_logic; -- Noncompliant
i1 : in std_logic;
o1 : out std_logic
);
end entity;
architecture rtl of fly is
begin
process (clk, rst) is
begin
if rst = '1' then
o1 <= '0';
elsif rising_edge(clk) then
if enable1 = '0' then
o1 <= i1;
end if;
end if;
end process;
end architecture;
With default regular expression: ^[a-z\d_]+_enable)|enable$
entity fly is
port (
clk : in std_logic;
rst : in std_logic;
enable : in std_logic; -- Compliant
i1 : in std_logic;
o1 : out std_logic
);
end entity;
architecture rtl of fly is
begin
process (clk, rst) is
begin
if rst = '1' then
o1 <= '0';
elsif rising_edge(clk) then
if enable = '0' then
o1 <= i1;
end if;
end if;
end process;
end architecture;