Both active-low and active-high enables should not be used for the same enable signal.
architecture rtl of fly is
begin
A: process (clk, rst) is
begin
if rst = '1' then
o1 <= '0';
elsif rising_edge(clk) then
if enable = '0' then -- Active-low enable
o1 <= i1;
end if;
end if;
end process;
B: process (clk, rst) is
begin
if rst = '1' then
o2 <= '0';
elsif rising_edge(clk) then
if enable = '1' then -- Active-high enable
o2 <= i2;
end if;
end if;
end process;
end architecture;
architecture rtl of fly is
begin
A: process (clk, rst) is
begin
if rst = '1' then
o1 <= '0';
elsif rising_edge(clk) then
if enable = '1' then -- Active-high enable
o1 <= i1;
end if;
end if;
end process;
B: process (clk, rst) is
begin
if rst = '1' then
o2 <= '0';
elsif rising_edge(clk) then
if enable = '1' then -- Active-high enable
o2 <= i2;
end if;
end if;
end process;
end architecture;