Why is this an issue?

To better understand clock usage, clock names should be preserved across the design.

How to fix it

Code examples

Noncompliant code example

With prefixToIgnore and suffixToIgnore parameters not set:

entity top is
  port(
    clk : in std_logic;
    ...
  )
end;

entity fly is
  port(
    i_myclock : in std_logic; -- Noncompliant: 'i_myclock' should be 'clk' instead
    ...
  )
end;

architecture rtl of top is
begin
  fly_i1 : entity work.fly(rtl)
  port map(
    i_myclock => clk, -- Noncompliant: 'i_myclock' should be 'clk' instead
    ...
  );
end;

With prefixToIgnore set to (i|o|io)_:

entity top is
  port(
    clk : in std_logic;
    ...
  )
end;

entity fly is
  port(
    i_myclock : in std_logic; -- Noncompliant: 'i_myclock' should be either 'clk' or 'i_clk'
    ...
  )
end;

architecture rtl of top is
begin
  fly_i1 : entity work.fly(rtl)
  port map(
    i_myclock => clk, -- Noncompliant: 'i_myclock' should be either 'clk' or 'i_clk'
    ...
  );
end;

Compliant solution

With prefixToIgnore and suffixToIgnore parameters not set:

entity top is
  port(
    clk : in std_logic;
    ...
  )
end;

entity fly is
  port(
    clk : in std_logic; -- Compliant
    ...
  )
end;

architecture rtl of top is
begin
  fly_i1 : entity work.fly(rtl)
  port map(
    clk => clk, -- Compliant
    ...
  );
end;

With prefixToIgnore set to (i|o|io)_:

entity top is
  port(
    clk : in std_logic;
    ...
  )
end;

entity fly is
  port(
    i_clk : in std_logic; -- Compliant
    ...
  )
end;

architecture rtl of top is
begin
  fly_i1 : entity work.fly(rtl)
  port map(
    i_clk => clk, -- Compliant
    ...
  );
end;