Why is this an issue?

For better readability, port clauses should be properly formatted:

How to fix it

Code examples

Noncompliant code example

With oneSingleWhitespace set to true:

entity e is
  port(a : in std_logic; -- Noncompliant: Write "port(" on its own line
       c : out std_logic); -- Noncompliant: Write closing parenthesis on its own line
end;

entity e is
  port(
    a : in std_logic; b : in std_logic; -- Noncompliant: Write each declaration on a dedicated line
    c : out std_logic
  );
end;

entity e is
  port(
    a: in std_logic;  -- Noncompliant: vertically align colons one whitespace after the longest signal name
    b : out std_logic
  );
end;

entity e is
  port(
    a :  in std_logic;  -- Noncompliant: Vertically align modes one whitespace after their preceding colon
    b : out std_logic
  );
end;

entity e is
  port(
    a : in std_logic;  -- Noncompliant: Vertically align types one whitespace after the longest mode
    b : out std_logic
  );
end;

Compliant solution

With oneSingleWhitespace set to true: Check vertical alignment and allow one single whitespace between columns.

entity e is
  port(
    a  : in    std_logic;
    b  : in    std_logic;
    c  : inout std_logic_vector;
    de : out   std_logic
  );
end;

With oneSingleWhitespace set to false: Check vertical alignment but the number of whitespaces between columns can be greater than one.

entity e is
  port(
    a    :   in        std_logic;
    b    :   in        std_logic;
    c    :   inout     std_logic_vector;
    de   :   out       std_logic
  );
end;