Clock Domain Crossings (CDC)

Count: 33

ID	Origin Flip-flop	Target Flip-flop
1	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg` Clock domain: clk_reg (rising)
2	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.next_opcode_reg` Clock domain: clk_reg (rising)
3	Signal: `u2_ddr.cycle_count2` Clock domain: CLK_50MHZ (falling)	Signal: `u2_ddr.write_active` Clock domain: clk_reg (rising)
4	Signal: `u2_ddr.cycle_count2` Clock domain: CLK_50MHZ (falling)	Signal: `u2_ddr.write_prev` Clock domain: clk_reg (rising)
5	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg` Clock domain: clk_reg (rising)
6	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u1_cpu.u4_reg_bank.intr_enable_reg` Clock domain: clk_reg (rising)
7	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg` Clock domain: clk_reg (rising)	Signal: `u2_ddr.byte_we_reg2` Clock domain: CLK_50MHZ (falling)
8	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg` Clock domain: clk_reg (rising)	Signal: `u2_ddr.byte_we_reg2` Clock domain: CLK_50MHZ (falling)
9	Signal: `clk_reg` Clock domain: CLK_50MHZ (rising)	Signal: `u2_ddr.byte_we_reg2` Clock domain: CLK_50MHZ (falling)
10	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg` Clock domain: clk_reg (rising)	Signal: `u2_ddr.data_write2` Clock domain: CLK_50MHZ (falling)
11	Signal: `u1_plama.u1_cpu.intr_signal` Clock domain: clk_reg (rising)	Signal: `u2_ddr.data_write2` Clock domain: CLK_50MHZ (falling)
12	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg` Clock domain: clk_reg (rising)	Signal: `u2_ddr.data_write2` Clock domain: CLK_50MHZ (falling)
13	Signal: `u1_plama.u1_cpu.intr_signal` Clock domain: clk_reg (rising)	Signal: `u2_ddr.data_write2` Clock domain: CLK_50MHZ (falling)
14	Signal: `clk_reg` Clock domain: CLK_50MHZ (rising)	Signal: `u2_ddr.data_write2` Clock domain: CLK_50MHZ (falling)
15	Signal: `u2_ddr.write_active` Clock domain: clk_reg (rising)	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)
16	Signal: `u2_ddr.data_write2` Clock domain: CLK_50MHZ (falling)	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)
17	Signal: `u2_ddr.write_active` Clock domain: clk_reg (rising)	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)
18	Signal: `u2_ddr.data_write2` Clock domain: CLK_50MHZ (falling)	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)
19	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.address_reg` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
20	Signal: `u1_plama.opt_cache2.u_cache.state_reg` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
21	Signal: `u2_ddr.bank_open` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
22	Signal: `u2_ddr.bank_open` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
23	Signal: `u2_ddr.bank_open` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
24	Signal: `u2_ddr.bank_open` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
25	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.byte_we_reg` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
26	Signal: `u2_ddr.write_prev` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
27	Signal: `u2_ddr.refresh_cnt` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
28	Signal: `u2_ddr.state_prev` Clock domain: clk_reg (rising)	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)
29	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg` Clock domain: clk_reg (rising)
30	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u1_cpu.u2_mem_ctrl.opcode_reg` Clock domain: clk_reg (rising)
31	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u2_ram.generic_ram.ram_proc.data` Clock domain: clk_reg (rising)
32	Signal: `u2_ddr.data_read` Clock domain: CLK_50MHZ (rising)	Signal: `u1_plama.u2_ram.generic_ram.ram_proc.data` Clock domain: clk_reg (rising)
33	Signal: `u2_ddr.cycle_count` Clock domain: CLK_50MHZ (rising)	Signal: `u2_ddr.cycle_count2` Clock domain: CLK_50MHZ (falling)