Clock Domains

Clock Management Module (CMM)

None identified.


All clocks should be generated within a unique clock management module (CMM). A dedicated CMM brings a lot in terms of reuse and portability. Because all vendor-specific clock elements are generated within the same module, it is easier to replace this module to target other FPGAs.

Clock Domains

Count: 3

Name: Origin

Graph

Rising

Falling

Details

clk_reg
  - clk_reg: plasma_3e.vhd#163 (Flip-flop)

Open Clock Hierarchy Graph

View Clock Domain Details

CLK_50MHZ
  - CLK_50MHZ: plasma_3e.vhd#24 (Port)

Open Clock Hierarchy Graph

View Clock Domain Details

A clock domain used for both rising and falling edges is counted as two separate clock domains.