Clock Domain Details

Summary

Name: Origin	Graph	Rising	Falling	Number of flip-flops using this clock domain	Number of instances using this clock domain
clk_reg - clk_reg: plasma_3e.vhd#163 (Flip-flop)		✔	✗	46/56 (82.14%)	11/15

Instances using this clock domain

Count: 11

Instance	Rising	Falling
TOP (plasma_3e)	✔	✗
TOP (plasma_3e) > u1_plama (plasma)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u1_pc_next (pc_next)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u2_mem_ctrl (mem_ctrl)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u4_reg_bank (reg_bank)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > u1_cpu (mlite_cpu) > u8_mult (mult)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > opt_cache2.u_cache (cache)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > u2_ram (ram)	✔	✗
TOP (plasma_3e) > u1_plama (plasma) > u3_uart (uart)	✔	✗
TOP (plasma_3e) > u2_ddr (ddr_ctrl)	✔	✗

Flip-flops using this clock domain

Count: 46

Rising-edge usage

Count: 46
cache.vhd#130
cache.vhd#167
ddr_ctrl.vhd#218
mem_ctrl.vhd#165
mlite_cpu.vhd#160
mult.vhd#99
pc_next.vhd#59
plasma.vhd#208
plasma_3e.vhd#251
ram.vhd#65
reg_bank.vhd#89
uart.vhd#63

Falling-edge usage

Count: 0

Note that there could be fewer source code locations than the number of flip-flops because several flip-flops can be inferred from the same piece of code.

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