Linty HDL Designer
v1.2.3
Summary Report
Design Hierarchy
Clock Domains
Reset Domains
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Finite State Machines (FSM)
Combinational Loops
Linty HDL Designer
v1.2.3
Instantiation - u2_mem_ctrl
View page source
Back to Module Report
Instantiation - u2_mem_ctrl
Summary
Name
Architecture
Description
u2_mem_ctrl
logic
Generics
Count: 0
Back to Module Report