Back to Package Report

Component - mlite_cpu

Summary

Name	Location	Description
mlite_cpu	mlite_pack.vhd#351

Generics

Count: 5

Name	Type	Default value	Description
memory_type	string	“XILINX_16X”
mult_type	string	“DEFAULT”
shifter_type	string	“DEFAULT”
alu_type	string	“DEFAULT”
pipeline_stages	natural	2

Ports

Count: 10

Name	Mode	Type	Description
clk	in	std_logic
reset_in	in	std_logic
intr_in	in	std_logic
address_next	out	std_logic_vector ( 31 downto 2 )
byte_we_next	out	std_logic_vector ( 3 downto 0 )
address	out	std_logic_vector ( 31 downto 2 )
byte_we	out	std_logic_vector ( 3 downto 0 )
data_w	out	std_logic_vector ( 31 downto 0 )
data_r	in	std_logic_vector ( 31 downto 0 )
mem_pause	in	std_logic

Back to Package Report