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Component - cache

Summary

Name	Location	Description
cache	mlite_pack.vhd#371

Generics

Count: 1

Name	Type	Default value	Description
memory_type	string	“DEFAULT”

Ports

Count: 9

Name	Mode	Type	Description
clk	in	std_logic
reset	in	std_logic
address_next	in	std_logic_vector ( 31 downto 2 )
byte_we_next	in	std_logic_vector ( 3 downto 0 )
cpu_address	in	std_logic_vector ( 31 downto 2 )
mem_busy	in	std_logic
cache_access	out	std_logic
cache_checking	out	std_logic
cache_miss	out	std_logic

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