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Component - reg_bank

Summary

Name	Location	Description
reg_bank	mlite_pack.vhd#260

Generics

Count: 1

Name	Type	Default value	Description
memory_type	string	“XILINX_16X”

Ports

Count: 10

Name	Mode	Type	Description
clk	in	std_logic
reset_in	in	std_logic
pause	in	std_logic
rs_index	in	std_logic_vector ( 5 downto 0 )
rt_index	in	std_logic_vector ( 5 downto 0 )
rd_index	in	std_logic_vector ( 5 downto 0 )
reg_source_out	out	std_logic_vector ( 31 downto 0 )
reg_target_out	out	std_logic_vector ( 31 downto 0 )
reg_dest_new	in	std_logic_vector ( 31 downto 0 )
intr_enable	out	std_logic

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