Design Hierarchy

Summary

Hierarchy	Modules	Instantiations
	15	15

Dependencies

Properly architecture your design to tend to a highly hierarchical design. Modules that instantiate too many other modules have likely too many responsibilities.

Instance	Modules	Instantiations
u1_cpu	Count: 8 alu bus_mux control mem_ctrl mult pc_next reg_bank shifter	Count: 8 u1_pc_next: pc_next (logic) u2_mem_ctrl: mem_ctrl (logic) u3_control: control (logic) u4_reg_bank: reg_bank (ram_block) u5_bus_mux: bus_mux (logic) u6_alu: alu (logic) u7_shifter: shifter (logic) u8_mult: mult (logic)
u1_plama	Count: 4 cache mlite_cpu ram uart	Count: 4 opt_cache2.u_cache: cache (logic) u1_cpu: mlite_cpu (logic) u2_ram: ram (logic) u3_uart: uart (logic)
plasma_3e (top)	Count: 2 ddr_ctrl plasma	Count: 2 u1_plama: plasma (logic) u2_ddr: ddr_ctrl (logic)
opt_cache2.u_cache
u1_pc_next
u2_ddr
u2_mem_ctrl
u2_ram
u3_control
u3_uart
u4_reg_bank
u5_bus_mux
u6_alu
u7_shifter
u8_mult

Note that instantiations from blackboxes or third-party IPs are not listed in this report.

VHDL Entities

Count: 20

Name	Location	Description	Details
alu	alu.vhd#16
bus_mux	bus_mux.vhd#22
cache	cache.vhd#21
control	control.vhd#27
ddr_ctrl	ddr_ctrl.vhd#57
eth_dma	eth_dma.vhd#22
mem_ctrl	mem_ctrl.vhd#17
mlite_cpu	mlite_cpu.vhd#74
mult	mult.vhd#45
pc_next	pc_next.vhd#16
pipeline	pipeline.vhd#18
plasma	plasma.vhd#39
plasma_3e	plasma_3e.vhd#19
plasma_if	plasma_if.vhd#18
ram	ram.vhd#23
ram	ram_xilinx.vhd#44
reg_bank	reg_bank.vhd#20
shifter	shifter.vhd#17
tbench	tbench.vhd#17
uart	uart.vhd#21

VHDL Packages

Count: 1

Name	Location	Description	Details
mlite_pack	mlite_pack.vhd#15