Finite State Machines (FSM)

Count: 2

ID	Name	Location	Graph	Reset State	States	Input Signals	Output Signals	Details
1	state_reg	cache.vhd#43		00	Count: 4 00 01 10 11	6	5
2	state_prev	ddr_ctrl.vhd#114		0000	Count: 9 0000 0001 0010 0011 0100 0101 0110 0111 1000	10	6