Back to FSM Report

FSM #2: state_prev

Summary

Name	Location	Graph	Reset State	States	Input Signals	Output Signals
state_prev	ddr_ctrl.vhd#114		0000	Count: 9 0000 0001 0010 0011 0100 0101 0110 0111 1000	10	6

Input Signals

Count: 10

Name	Declaration
SD_BA	ddr_ctrl.vhd#76
active	ddr_ctrl.vhd#67
address	ddr_ctrl.vhd#63
bank_open	ddr_ctrl.vhd#124
byte_we	ddr_ctrl.vhd#64
ddr_proc.bank_index	ddr_ctrl.vhd#139
no_start	ddr_ctrl.vhd#68
no_stop	ddr_ctrl.vhd#69
refresh_cnt	ddr_ctrl.vhd#115
write_prev	ddr_ctrl.vhd#119

Output Signals

Count: 6

Name	Declaration
SD_CAS	ddr_ctrl.vhd#80
SD_RAS	ddr_ctrl.vhd#79
SD_WE	ddr_ctrl.vhd#81
ddr_proc.command	ddr_ctrl.vhd#138
ddr_proc.state_current	ddr_ctrl.vhd#140
pause	ddr_ctrl.vhd#70

Transition table

From	To	Input Control Signals
0000	0000	active: ddr_ctrl.vhd#67
0000	0000	active: ddr_ctrl.vhd#67 byte_we: ddr_ctrl.vhd#64
0000	0001	active: ddr_ctrl.vhd#67 byte_we: ddr_ctrl.vhd#64
0001	0001	active: ddr_ctrl.vhd#67 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
0001	0010	active: ddr_ctrl.vhd#67 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
0001	0111	refresh_cnt: ddr_ctrl.vhd#115
0010	0011
0011	0010	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
0011	0011	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 byte_we: ddr_ctrl.vhd#64 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
0011	0011	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 byte_we: ddr_ctrl.vhd#64 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
0011	0011	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
0011	0011	active: ddr_ctrl.vhd#67 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115
0011	0011	refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
0011	0100	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 byte_we: ddr_ctrl.vhd#64 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
0011	0111	SD_BA: ddr_ctrl.vhd#76 active: ddr_ctrl.vhd#67 address: ddr_ctrl.vhd#63 bank_open: ddr_ctrl.vhd#124 ddr_proc.bank_index: ddr_ctrl.vhd#139 no_start: ddr_ctrl.vhd#68 refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
0011	0111	refresh_cnt: ddr_ctrl.vhd#115 write_prev: ddr_ctrl.vhd#119
0100	0101
0101	0110
0110	0011	no_stop: ddr_ctrl.vhd#69
0110	0110	no_stop: ddr_ctrl.vhd#69
0111	1000
1000	0001

Back to FSM Report