Reset Domains

Reset Management Module (RMM)

mlite_cpu instantiated as u1_cpu


All global resets should be generated within a unique reset management module (RMM). A dedicated RMM brings a lot in terms of reuse and portability. Because all vendor-specific reset elements are generated within the same module, it is easier to replace this module to target other FPGAs.

Global Reset Domains

Count: 2

Name: Origin

Graph

Asynchronous

Synchronous

Active High

Active Low

Details

ROT_CENTER
  - ROT_CENTER: plasma_3e.vhd#73 (Port)

Open Reset Hierarchy Graph

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View Reset Domain Details

Complex: u1_plama.u1_cpu.u1_pc_next.reset_in
  - ROT_CENTER: plasma_3e.vhd#73 (Port)
  - u1_plama.u1_cpu.reset_reg: mlite_cpu.vhd#160 (Flip-flop)

Open Reset Hierarchy Graph

✔

✗

✔

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View Reset Domain Details

A reset domain is considered as global if:

  • It is used in several modules.

  • Or it is used in a single module and by at least 20% of the flip-flops in the design.

Local Reset Domains

Count: 0