# Clock Domains

## Clock Management Module (CMM)

None identified.

<br>

*All clocks should be generated within a unique clock management module (CMM).*
*A dedicated CMM brings a lot in terms of reuse and portability. Because all vendor-specific clock elements are generated within the same module, it is easier to replace this module to target other FPGAs.*



## Clock Domains

Count: **3**

| Name: Origin | Graph | Rising | Falling | Details |
| --- | :---: | :---: | :---: | :---: |
|**<linty-anchor href="/plasma_3e.vhd#140">clk_reg</linty-anchor>**<br>&nbsp;&nbsp;-&nbsp;**clk_reg**: <linty-anchor href="//plasma_3e.vhd#163"> plasma_3e.vhd#163 (Flip-flop)</linty-anchor>|<a href="/graphs/clock_hierarchy_graph.html"><img title="Open Clock Hierarchy Graph" src="/_static/images/icon_graph.png" style="max-height: 25px; width: auto;" alt="Open Clock Hierarchy Graph"></a>|&#10004;|&#10007;|[<img title="View Clock Domain Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Clock Domain Details">](clock_domains/clock_domain_1.md)|
|**<linty-anchor href="/plasma_3e.vhd#24">CLK_50MHZ</linty-anchor>**<br>&nbsp;&nbsp;-&nbsp;**CLK_50MHZ**: <linty-anchor href="//plasma_3e.vhd#24"> plasma_3e.vhd#24 (Port)</linty-anchor>|<a href="/graphs/clock_hierarchy_graph.html"><img title="Open Clock Hierarchy Graph" src="/_static/images/icon_graph.png" style="max-height: 25px; width: auto;" alt="Open Clock Hierarchy Graph"></a>|&#10004;|&#10004;|[<img title="View Clock Domain Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Clock Domain Details">](clock_domains/clock_domain_2.md)|


*A clock domain used for both rising and falling edges is counted as two separate clock domains.*

