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# Entity - ram

## Summary

| Name | Location | Description |
| --- | --- | --- |
|ram|<linty-anchor href="//ram.vhd#23">ram.vhd#23</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| u2_ram | <linty-anchor href="/plasma.vhd#256">plasma.vhd#256</linty-anchor> |  | [<img title="View Instantiation Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_15/instantiation_1.md) |


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//ram.vhd#24">memory_type</linty-anchor>|string|"DEFAULT"||
## Ports

Count: 6

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//ram.vhd#25">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//ram.vhd#26">enable</linty-anchor>|in|std_logic||
|<linty-anchor href="//ram.vhd#27">write_byte_enable</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//ram.vhd#28">address</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//ram.vhd#29">data_write</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//ram.vhd#30">data_read</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||


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