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# Entity - ram

## Summary

| Name | Location | Description |
| --- | --- | --- |
|ram|<linty-anchor href="//ram_xilinx.vhd#44">ram_xilinx.vhd#44</linty-anchor>||
## Instantiations

Count: 0

## Generics

Count: 2

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//ram_xilinx.vhd#45">memory_type</linty-anchor>|string|"DEFAULT"||
|<linty-anchor href="//ram_xilinx.vhd#47">block_count</linty-anchor>|integer|1||
## Ports

Count: 6

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//ram_xilinx.vhd#48">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//ram_xilinx.vhd#49">enable</linty-anchor>|in|std_logic||
|<linty-anchor href="//ram_xilinx.vhd#50">write_byte_enable</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//ram_xilinx.vhd#51">address</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//ram_xilinx.vhd#52">data_write</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//ram_xilinx.vhd#53">data_read</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||


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