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# Entity - reg_bank

## Summary

| Name | Location | Description |
| --- | --- | --- |
|reg_bank|<linty-anchor href="//reg_bank.vhd#20">reg_bank.vhd#20</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| u4_reg_bank | <linty-anchor href="/mlite_cpu.vhd#235">mlite_cpu.vhd#235</linty-anchor> |  | [<img title="View Instantiation Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_17/instantiation_1.md) |


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//reg_bank.vhd#21">memory_type</linty-anchor>|string|"XILINX_16X"||
## Ports

Count: 10

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//reg_bank.vhd#22">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//reg_bank.vhd#23">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//reg_bank.vhd#24">pause</linty-anchor>|in|std_logic||
|<linty-anchor href="//reg_bank.vhd#25">rs_index</linty-anchor>|in|std_logic_vector ( 5 downto 0 )||
|<linty-anchor href="//reg_bank.vhd#26">rt_index</linty-anchor>|in|std_logic_vector ( 5 downto 0 )||
|<linty-anchor href="//reg_bank.vhd#27">rd_index</linty-anchor>|in|std_logic_vector ( 5 downto 0 )||
|<linty-anchor href="//reg_bank.vhd#28">reg_source_out</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//reg_bank.vhd#29">reg_target_out</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//reg_bank.vhd#30">reg_dest_new</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//reg_bank.vhd#31">intr_enable</linty-anchor>|out|std_logic||


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