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# Entity - ddr_ctrl

## Summary

| Name | Location | Description |
| --- | --- | --- |
|ddr_ctrl|<linty-anchor href="//ddr_ctrl.vhd#57">ddr_ctrl.vhd#57</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| u2_ddr | <linty-anchor href="/plasma_3e.vhd#215">plasma_3e.vhd#215</linty-anchor> |  | [<img title="View Instantiation Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_5/instantiation_1.md) |


## Generics

Count: 0

## Ports

Count: 25

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//ddr_ctrl.vhd#59">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#60">clk_2x</linty-anchor>|in|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#61">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#63">address</linty-anchor>|in|std_logic_vector ( 25 downto 2 )||
|<linty-anchor href="//ddr_ctrl.vhd#64">byte_we</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//ddr_ctrl.vhd#65">data_w</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//ddr_ctrl.vhd#66">data_r</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//ddr_ctrl.vhd#67">active</linty-anchor>|in|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#68">no_start</linty-anchor>|in|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#69">no_stop</linty-anchor>|in|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#70">pause</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#72">SD_CK_P</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#73">SD_CK_N</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#74">SD_CKE</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#76">SD_BA</linty-anchor>|out|std_logic_vector ( 1 downto 0 )||
|<linty-anchor href="//ddr_ctrl.vhd#77">SD_A</linty-anchor>|out|std_logic_vector ( 12 downto 0 )||
|<linty-anchor href="//ddr_ctrl.vhd#78">SD_CS</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#79">SD_RAS</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#80">SD_CAS</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#81">SD_WE</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#83">SD_DQ</linty-anchor>|inout|std_logic_vector ( 15 downto 0 )||
|<linty-anchor href="//ddr_ctrl.vhd#84">SD_UDM</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#85">SD_UDQS</linty-anchor>|inout|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#86">SD_LDM</linty-anchor>|out|std_logic||
|<linty-anchor href="//ddr_ctrl.vhd#87">SD_LDQS</linty-anchor>|inout|std_logic||


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