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# Entity - mem_ctrl

## Summary

| Name | Location | Description |
| --- | --- | --- |
|mem_ctrl|<linty-anchor href="//mem_ctrl.vhd#17">mem_ctrl.vhd#17</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| u2_mem_ctrl | <linty-anchor href="/mlite_cpu.vhd#194">mlite_cpu.vhd#194</linty-anchor> |  | [<img title="View Instantiation Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_7/instantiation_1.md) |


## Generics

Count: 0

## Ports

Count: 17

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mem_ctrl.vhd#18">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mem_ctrl.vhd#19">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mem_ctrl.vhd#20">pause_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mem_ctrl.vhd#21">nullify_op</linty-anchor>|in|std_logic||
|<linty-anchor href="//mem_ctrl.vhd#22">address_pc</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mem_ctrl.vhd#23">opcode_out</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mem_ctrl.vhd#25">address_in</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mem_ctrl.vhd#26">mem_source</linty-anchor>|in|mem_source_type||
|<linty-anchor href="//mem_ctrl.vhd#27">data_write</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mem_ctrl.vhd#28">data_read</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mem_ctrl.vhd#29">pause_out</linty-anchor>|out|std_logic||
|<linty-anchor href="//mem_ctrl.vhd#31">address_next</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mem_ctrl.vhd#32">byte_we_next</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mem_ctrl.vhd#34">address</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mem_ctrl.vhd#35">byte_we</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mem_ctrl.vhd#36">data_w</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mem_ctrl.vhd#37">data_r</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||


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