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# Entity - mlite_cpu

## Summary

| Name | Location | Description |
| --- | --- | --- |
|mlite_cpu|<linty-anchor href="//mlite_cpu.vhd#74">mlite_cpu.vhd#74</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| u1_cpu | <linty-anchor href="/plasma.vhd#126">plasma.vhd#126</linty-anchor> |  | [<img title="View Instantiation Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_8/instantiation_1.md) |


## Generics

Count: 5

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_cpu.vhd#75">memory_type</linty-anchor>|string|"XILINX_16X"||
|<linty-anchor href="//mlite_cpu.vhd#76">mult_type</linty-anchor>|string|"DEFAULT"||
|<linty-anchor href="//mlite_cpu.vhd#77">shifter_type</linty-anchor>|string|"DEFAULT"||
|<linty-anchor href="//mlite_cpu.vhd#78">alu_type</linty-anchor>|string|"DEFAULT"||
|<linty-anchor href="//mlite_cpu.vhd#79">pipeline_stages</linty-anchor>|natural|2||
## Ports

Count: 10

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_cpu.vhd#80">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_cpu.vhd#81">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_cpu.vhd#82">intr_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_cpu.vhd#84">address_next</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_cpu.vhd#85">byte_we_next</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_cpu.vhd#87">address</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_cpu.vhd#88">byte_we</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_cpu.vhd#89">data_w</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_cpu.vhd#90">data_r</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_cpu.vhd#91">mem_pause</linty-anchor>|in|std_logic||


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