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# Component - mlite_cpu

## Summary

| Name | Location | Description |
| --- | --- | --- |
|mlite_cpu|<linty-anchor href="//mlite_pack.vhd#351">mlite_pack.vhd#351</linty-anchor>||


## Generics

Count: 5

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#352">memory_type</linty-anchor>|string|"XILINX_16X"||
|<linty-anchor href="//mlite_pack.vhd#353">mult_type</linty-anchor>|string|"DEFAULT"||
|<linty-anchor href="//mlite_pack.vhd#354">shifter_type</linty-anchor>|string|"DEFAULT"||
|<linty-anchor href="//mlite_pack.vhd#355">alu_type</linty-anchor>|string|"DEFAULT"||
|<linty-anchor href="//mlite_pack.vhd#356">pipeline_stages</linty-anchor>|natural|2||


## Ports

Count: 10

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#357">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#358">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#359">intr_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#361">address_next</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#362">byte_we_next</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#364">address</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#365">byte_we</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#366">data_w</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#367">data_r</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#368">mem_pause</linty-anchor>|in|std_logic||


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