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# Component - cache

## Summary

| Name | Location | Description |
| --- | --- | --- |
|cache|<linty-anchor href="//mlite_pack.vhd#371">mlite_pack.vhd#371</linty-anchor>||


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#372">memory_type</linty-anchor>|string|"DEFAULT"||


## Ports

Count: 9

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#373">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#374">reset</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#375">address_next</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#376">byte_we_next</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#377">cpu_address</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#378">mem_busy</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#380">cache_access</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#381">cache_checking</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#382">cache_miss</linty-anchor>|out|std_logic||


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