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# Component - ram

## Summary

| Name | Location | Description |
| --- | --- | --- |
|ram|<linty-anchor href="//mlite_pack.vhd#385">mlite_pack.vhd#385</linty-anchor>||


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#386">memory_type</linty-anchor>|string|"DEFAULT"||


## Ports

Count: 6

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#387">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#388">enable</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#389">write_byte_enable</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#390">address</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#391">data_write</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#392">data_read</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||


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