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# Component - uart

## Summary

| Name | Location | Description |
| --- | --- | --- |
|uart|<linty-anchor href="//mlite_pack.vhd#395">mlite_pack.vhd#395</linty-anchor>||


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#396">log_file</linty-anchor>|string|"UNUSED"||


## Ports

Count: 10

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#397">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#398">reset</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#399">enable_read</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#400">enable_write</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#401">data_in</linty-anchor>|in|std_logic_vector ( 7 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#402">data_out</linty-anchor>|out|std_logic_vector ( 7 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#403">uart_read</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#404">uart_write</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#405">busy_write</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#406">data_avail</linty-anchor>|out|std_logic||


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