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# Component - eth_dma

## Summary

| Name | Location | Description |
| --- | --- | --- |
|eth_dma|<linty-anchor href="//mlite_pack.vhd#409">mlite_pack.vhd#409</linty-anchor>||


## Generics

Count: 0



## Ports

Count: 21

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#410">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#411">reset</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#412">enable_eth</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#413">select_eth</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#414">rec_isr</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#415">send_isr</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#417">address</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#418">byte_we</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#419">data_write</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#420">data_read</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#421">pause_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#423">mem_address</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#424">mem_byte_we</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#425">data_w</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#426">pause_out</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#428">E_RX_CLK</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#429">E_RX_DV</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#430">E_RXD</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#431">E_TX_CLK</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#432">E_TX_EN</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#433">E_TXD</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||


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