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# Component - ddr_ctrl

## Summary

| Name | Location | Description |
| --- | --- | --- |
|ddr_ctrl|<linty-anchor href="//mlite_pack.vhd#458">mlite_pack.vhd#458</linty-anchor>||


## Generics

Count: 0



## Ports

Count: 25

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#459">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#460">clk_2x</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#461">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#463">address</linty-anchor>|in|std_logic_vector ( 25 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#464">byte_we</linty-anchor>|in|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#465">data_w</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#466">data_r</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#467">active</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#468">no_start</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#469">no_stop</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#470">pause</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#472">SD_CK_P</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#473">SD_CK_N</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#474">SD_CKE</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#476">SD_BA</linty-anchor>|out|std_logic_vector ( 1 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#477">SD_A</linty-anchor>|out|std_logic_vector ( 12 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#478">SD_CS</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#479">SD_RAS</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#480">SD_CAS</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#481">SD_WE</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#483">SD_DQ</linty-anchor>|inout|std_logic_vector ( 15 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#484">SD_UDM</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#485">SD_UDQS</linty-anchor>|inout|std_logic||
|<linty-anchor href="//mlite_pack.vhd#486">SD_LDM</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#487">SD_LDQS</linty-anchor>|inout|std_logic||


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