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# Component - RAM16X1D

## Summary

| Name | Location | Description |
| --- | --- | --- |
|RAM16X1D|<linty-anchor href="//mlite_pack.vhd#164">mlite_pack.vhd#164</linty-anchor>||


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#166">INIT</linty-anchor>|bit_vector|X"0000"||


## Ports

Count: 13

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#168">DPO</linty-anchor>|out|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#169">SPO</linty-anchor>|out|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#170">A0</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#171">A1</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#172">A2</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#173">A3</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#174">D</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#175">DPRA0</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#176">DPRA1</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#177">DPRA2</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#178">DPRA3</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#179">WCLK</linty-anchor>|in|STD_ULOGIC||
|<linty-anchor href="//mlite_pack.vhd#180">WE</linty-anchor>|in|STD_ULOGIC||


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