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# Component - mem_ctrl

## Summary

| Name | Location | Description |
| --- | --- | --- |
|mem_ctrl|<linty-anchor href="//mlite_pack.vhd#218">mlite_pack.vhd#218</linty-anchor>||


## Generics

Count: 0



## Ports

Count: 17

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#219">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#220">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#221">pause_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#222">nullify_op</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#223">address_pc</linty-anchor>|in|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#224">opcode_out</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#226">address_in</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#227">mem_source</linty-anchor>|in|mem_source_type||
|<linty-anchor href="//mlite_pack.vhd#228">data_write</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#229">data_read</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#230">pause_out</linty-anchor>|out|std_logic||
|<linty-anchor href="//mlite_pack.vhd#232">address_next</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#233">byte_we_next</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#235">address</linty-anchor>|out|std_logic_vector ( 31 downto 2 )||
|<linty-anchor href="//mlite_pack.vhd#236">byte_we</linty-anchor>|out|std_logic_vector ( 3 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#237">data_w</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#238">data_r</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||


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