[Back to Package Report](../package_1.md#component-definitions)

<br>

# Component - reg_bank

## Summary

| Name | Location | Description |
| --- | --- | --- |
|reg_bank|<linty-anchor href="//mlite_pack.vhd#260">mlite_pack.vhd#260</linty-anchor>||


## Generics

Count: 1

| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#261">memory_type</linty-anchor>|string|"XILINX_16X"||


## Ports

Count: 10

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//mlite_pack.vhd#262">clk</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#263">reset_in</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#264">pause</linty-anchor>|in|std_logic||
|<linty-anchor href="//mlite_pack.vhd#265">rs_index</linty-anchor>|in|std_logic_vector ( 5 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#266">rt_index</linty-anchor>|in|std_logic_vector ( 5 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#267">rd_index</linty-anchor>|in|std_logic_vector ( 5 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#268">reg_source_out</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#269">reg_target_out</linty-anchor>|out|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#270">reg_dest_new</linty-anchor>|in|std_logic_vector ( 31 downto 0 )||
|<linty-anchor href="//mlite_pack.vhd#271">intr_enable</linty-anchor>|out|std_logic||


<br>

[Back to Package Report](../package_1.md#component-definitions)