# Design Hierarchy

## Summary

| Hierarchy | Modules | Instantiations |
| :---: | --- | --- |
| <a href="/graphs/design_hierarchy_graph.html"><img title="Open Design Hierarchy Graph" src="/_static/images/icon_graph.png" style="max-height: 25px; width: auto;" alt="Open Design Hierarchy Graph"></a> | 15 | 15 |


## Dependencies

Properly architecture your design to tend to a highly hierarchical design. Modules that instantiate too many other modules have likely too many responsibilities.

| Instance | Modules | Instantiations |
| --- | --- | --- |
|<linty-anchor href="/plasma.vhd#126">u1_cpu</linty-anchor>|Count: 8<br><linty-anchor href="/alu.vhd#16">alu</linty-anchor><br><linty-anchor href="/bus_mux.vhd#22">bus_mux</linty-anchor><br><linty-anchor href="/control.vhd#27">control</linty-anchor><br><linty-anchor href="/mem_ctrl.vhd#17">mem_ctrl</linty-anchor><br><linty-anchor href="/mult.vhd#45">mult</linty-anchor><br><linty-anchor href="/pc_next.vhd#16">pc_next</linty-anchor><br><linty-anchor href="/reg_bank.vhd#20">reg_bank</linty-anchor><br><linty-anchor href="/shifter.vhd#17">shifter</linty-anchor>|Count: 8<br><linty-anchor href="/mlite_cpu.vhd#182">u1_pc_next</linty-anchor>: <linty-anchor href="/pc_next.vhd#16">pc_next</linty-anchor> (<linty-anchor href="/pc_next.vhd#29">logic</linty-anchor>)<br><linty-anchor href="/mlite_cpu.vhd#194">u2_mem_ctrl</linty-anchor>: <linty-anchor href="/mem_ctrl.vhd#17">mem_ctrl</linty-anchor> (<linty-anchor href="/mem_ctrl.vhd#40">logic</linty-anchor>)<br><linty-anchor href="/mlite_cpu.vhd#217">u3_control</linty-anchor>: <linty-anchor href="/control.vhd#27">control</linty-anchor> (<linty-anchor href="/control.vhd#46">logic</linty-anchor>)<br><linty-anchor href="/mlite_cpu.vhd#235">u4_reg_bank</linty-anchor>: <linty-anchor href="/reg_bank.vhd#20">reg_bank</linty-anchor> (<linty-anchor href="/reg_bank.vhd#41">ram_block</linty-anchor>)<br><linty-anchor href="/mlite_cpu.vhd#249">u5_bus_mux</linty-anchor>: <linty-anchor href="/bus_mux.vhd#22">bus_mux</linty-anchor> (<linty-anchor href="/bus_mux.vhd#43">logic</linty-anchor>)<br><linty-anchor href="/mlite_cpu.vhd#269">u6_alu</linty-anchor>: <linty-anchor href="/alu.vhd#16">alu</linty-anchor> (<linty-anchor href="/alu.vhd#25">logic</linty-anchor>)<br><linty-anchor href="/mlite_cpu.vhd#277">u7_shifter</linty-anchor>: <linty-anchor href="/shifter.vhd#17">shifter</linty-anchor> (<linty-anchor href="/shifter.vhd#25">logic</linty-anchor>)<br><linty-anchor href="/mlite_cpu.vhd#285">u8_mult</linty-anchor>: <linty-anchor href="/mult.vhd#45">mult</linty-anchor> (<linty-anchor href="/mult.vhd#55">logic</linty-anchor>)<br>|
|<linty-anchor href="/plasma_3e.vhd#190">u1_plama</linty-anchor>|Count: 4<br><linty-anchor href="/cache.vhd#21">cache</linty-anchor><br><linty-anchor href="/mlite_cpu.vhd#74">mlite_cpu</linty-anchor><br><linty-anchor href="/ram.vhd#23">ram</linty-anchor><br><linty-anchor href="/uart.vhd#21">uart</linty-anchor>|Count: 4<br><linty-anchor href="/plasma.vhd#151">opt_cache2.u_cache</linty-anchor>: <linty-anchor href="/cache.vhd#21">cache</linty-anchor> (<linty-anchor href="/cache.vhd#36">logic</linty-anchor>)<br><linty-anchor href="/plasma.vhd#126">u1_cpu</linty-anchor>: <linty-anchor href="/mlite_cpu.vhd#74">mlite_cpu</linty-anchor> (<linty-anchor href="/mlite_cpu.vhd#94">logic</linty-anchor>)<br><linty-anchor href="/plasma.vhd#256">u2_ram</linty-anchor>: <linty-anchor href="/ram.vhd#23">ram</linty-anchor> (<linty-anchor href="/ram.vhd#33">logic</linty-anchor>)<br><linty-anchor href="/plasma.vhd#266">u3_uart</linty-anchor>: <linty-anchor href="/uart.vhd#21">uart</linty-anchor> (<linty-anchor href="/uart.vhd#35">logic</linty-anchor>)<br>|
|<linty-anchor href="/plasma_3e.vhd#19">plasma_3e (top)</linty-anchor>|Count: 2<br><linty-anchor href="/ddr_ctrl.vhd#57">ddr_ctrl</linty-anchor><br><linty-anchor href="/plasma.vhd#39">plasma</linty-anchor>|Count: 2<br><linty-anchor href="/plasma_3e.vhd#190">u1_plama</linty-anchor>: <linty-anchor href="/plasma.vhd#39">plasma</linty-anchor> (<linty-anchor href="/plasma.vhd#62">logic</linty-anchor>)<br><linty-anchor href="/plasma_3e.vhd#215">u2_ddr</linty-anchor>: <linty-anchor href="/ddr_ctrl.vhd#57">ddr_ctrl</linty-anchor> (<linty-anchor href="/ddr_ctrl.vhd#90">logic</linty-anchor>)<br>|
|<linty-anchor href="/plasma.vhd#151">opt_cache2.u_cache</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#182">u1_pc_next</linty-anchor>|||
|<linty-anchor href="/plasma_3e.vhd#215">u2_ddr</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#194">u2_mem_ctrl</linty-anchor>|||
|<linty-anchor href="/plasma.vhd#256">u2_ram</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#217">u3_control</linty-anchor>|||
|<linty-anchor href="/plasma.vhd#266">u3_uart</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#235">u4_reg_bank</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#249">u5_bus_mux</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#269">u6_alu</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#277">u7_shifter</linty-anchor>|||
|<linty-anchor href="/mlite_cpu.vhd#285">u8_mult</linty-anchor>|||


Note that instantiations from blackboxes or third-party IPs are not listed in this report.

## VHDL Entities

Count: 20

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
|alu|<linty-anchor href="//alu.vhd#16">alu.vhd#16</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_1.md)|
|bus_mux|<linty-anchor href="//bus_mux.vhd#22">bus_mux.vhd#22</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_2.md)|
|cache|<linty-anchor href="//cache.vhd#21">cache.vhd#21</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_3.md)|
|control|<linty-anchor href="//control.vhd#27">control.vhd#27</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_4.md)|
|ddr_ctrl|<linty-anchor href="//ddr_ctrl.vhd#57">ddr_ctrl.vhd#57</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_5.md)|
|eth_dma|<linty-anchor href="//eth_dma.vhd#22">eth_dma.vhd#22</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_6.md)|
|mem_ctrl|<linty-anchor href="//mem_ctrl.vhd#17">mem_ctrl.vhd#17</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_7.md)|
|mlite_cpu|<linty-anchor href="//mlite_cpu.vhd#74">mlite_cpu.vhd#74</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_8.md)|
|mult|<linty-anchor href="//mult.vhd#45">mult.vhd#45</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_9.md)|
|pc_next|<linty-anchor href="//pc_next.vhd#16">pc_next.vhd#16</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_10.md)|
|pipeline|<linty-anchor href="//pipeline.vhd#18">pipeline.vhd#18</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_11.md)|
|plasma|<linty-anchor href="//plasma.vhd#39">plasma.vhd#39</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_12.md)|
|plasma_3e|<linty-anchor href="//plasma_3e.vhd#19">plasma_3e.vhd#19</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_13.md)|
|plasma_if|<linty-anchor href="//plasma_if.vhd#18">plasma_if.vhd#18</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_14.md)|
|ram|<linty-anchor href="//ram.vhd#23">ram.vhd#23</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_15.md)|
|ram|<linty-anchor href="//ram_xilinx.vhd#44">ram_xilinx.vhd#44</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_16.md)|
|reg_bank|<linty-anchor href="//reg_bank.vhd#20">reg_bank.vhd#20</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_17.md)|
|shifter|<linty-anchor href="//shifter.vhd#17">shifter.vhd#17</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_18.md)|
|tbench|<linty-anchor href="//tbench.vhd#17">tbench.vhd#17</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_19.md)|
|uart|<linty-anchor href="//uart.vhd#21">uart.vhd#21</linty-anchor>||[<img title="View VHDL Entity Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Entity Details">](design/module_20.md)|


## VHDL Packages

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
|mlite_pack|<linty-anchor href="//mlite_pack.vhd#15">mlite_pack.vhd#15</linty-anchor>||[<img title="View VHDL Package Details" src="/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View VHDL Package Details">](design/package_1.md)|


